In general, the mask pattern forming technique used in a semiconductor fabrication process has an important effect on the accuracy of patterns formed on a semiconductor substrate. In particular, as the degree of integration of the patterns of semiconductor devices increases, spaces for optical proximity correction patterns become insufficient, and unwanted pattern bridges occur between lines during a lithography exposing process. Therefore, characteristics of the semiconductor device may be degraded.
On the other hand, by using semiconductor photolithography, masks can be designed with high accuracy, so that the amount of light passing through the masks can be suitably adjusted. In addition, an optical proximity correction technique and a phase shifting mask technique have been proposed. Further, various approaches for minimizing light distortion due to mask patterns have been proposed.
Recently, a chemical amplifying resist has been developed. The chemical amplifying resist is sensitive to 248 nm or 194 nm extreme ultra-violet (EUV) light. By using the chemical amplifying resist, the resolution can be further improved. In particular, by using dummy patterns separated from main patterns, the optical proximity effect can be controlled to improve the resolution.
FIG. 1 is a schematic illustration showing a portion of a conventional semiconductor device mask corresponding to cells in a static random access memory (SRAM). Referring to FIG. 1, cell patterns 3 are repeatedly disposed. In the case of cell patterns having a dark tone, image contours 4 occur, depending on the intensity of the light passing though the mask. In FIG. 1, three image contours 4 are shown reflecting three different light intensities. The outmost contour corresponds to a case where the exposing light is insufficient. If the exposing light is too insufficient, a pattern bridge is first formed at a region 7 between the cell patterns 3. The region 7 is, therefore, defined as a threshold region for limiting the pattern resolution and the exposing process margin. The process margin in the cross section taken along line A-B is smallest.
FIG. 2 is a schematic illustration showing pattern bridge problems in end portions of lines of a conventional semiconductor device mask. In general, fine auxiliary patterns 5 and 6 are disposed at positions separated by a predetermined distance from the end portions of lines in order to maximally extend the lines. As described above, if the exposing light is insufficient, pattern bridges may occur at regions A1, B1, and C1 in a memory cell. In the example of FIG. 2, the memory cell includes repeated cell patterns 3 and driving transistors 1 disposed perpendicular to the cell patterns 3. The regions A1 are regions between the driving transistors 1 and NMOS cells; the regions B1 are regions between the driving transistors 1 and PMOS cells; and the regions C1 are regions between the cell patterns 3 in the horizontal direction.
As mentioned above, fine auxiliary patterns 5, 6 are disposed at the regions A1 and B1 in order to extend the end portions of the lines. Since the occurrence of pattern bridges at the region C1 are particularly problematic, fine auxiliary patterns are not inserted into the regions C1.
Pattern resolution is defined by the following Equation 1 (Rayleigh's Equation):R=k·λ/NA  [Equation 1]
In this equation, k is a constant; λ is a wavelength of an illuminated light of an illumination system; and NA is a diameter of a lens of the illumination system. Assuming that k, λ, and NA are 0.5, 0.248, and 0.66, respectively, the obtained resolution R is 0.19 μm. If a fine pattern having a line width less than the obtained resolution is independently applied to a mask, a pattern where light physically passes only though the mask but does not appear in the photoresist material can be defined.
FIG. 3 is a schematic illustration showing overlapped contour images 4 in a case where the conventional mask of FIG. 2 is used for an exposing process. In FIG. 3, the contour images corresponding to a range of exposing conditions from an optimal exposing condition to an insufficient exposing condition are depicted. In FIG. 3, the outmost image 4 corresponds to the insufficient exposing condition. In addition, line G-H indicates an end portion of a cell line where a pattern bridge occurs.
In addition, if the line width increases due to a processing bias, or if the polarization degree of a semiconductor device is not good, a problem occurs in that a deviation may occur depending on the positions.